CS5342

DS608PP2

17

4.2.3

Master Clock

The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also

an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 3 shows a list-

ing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and

the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with

a fast MCLK (768x, 384x, 192x for Single, Double, and Quad Speed Modes respectively).

4.3

Serial Audio Interface

level on SDOUT (pin 4). A 10 k

to GND is needed to select Left Justified format. Please see Figures 13 through 16 on page 12, for more information

on the required timing for the two serial audio interface formats.

Single Speed Mode

Double Speed Mode

Quad Speed Mode

MCLK/LRCK Ratio

384x, 768x

192x, 384x

96x*, 192x

* Quad Speed, 96x only available in Master Mode.

Table 3. Master Clock (MCLK) Ratios

SAMPLE RATE (kHz)

MCLK (MHz)

32

12.288

44.1

16.9344

33.8688

48

18.432

36.864

64

12.288

88.2

16.9344

33.8688

96

18.432

36.864

192

36.864

Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates

Figure 19. Left-Justified Serial Audio Interface

SDATA

23 22

7

6

23 22

SCLK

LRCK

23 22

54

32

10

8

76

54

32

10

8

9

9

Left Channel

Right Channel

SDATA

23 22

8

7

23 22

SCLK

LRCK

23 22

65

43

21

0

87

65

43

21

0

9

9

Left Channel

Right Channel