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PMWD30UN датащи(PDF) 2 Page - NXP Semiconductors

номер детали PMWD30UN
подробное описание детали  Dual uTrenchMOS ultra low level FET
PDF  12 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PMWD30UN датащи(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
PMWD30UN
Dual
µTrenchMOS™ ultra low level FET
Product data
Rev. 01 — 22 January 2003
2 of 12
9397 750 10835
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3.
Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage (DC)
25
°C ≤ T
j ≤ 150 °C
-
30
V
VDGR
drain-gate voltage
25
°C ≤ T
j ≤ 150 °C; RGS =20kΩ
-30
V
VGS
gate-source voltage
-
±10
V
ID
drain current (DC)
Tsp =25 °C; VGS = 4.5 V; Figure 2 and 3
-5
A
Tsp = 100 °C; VGS = 4.5 V; Figure 2
-3
A
IDM
peak drain current
Tsp =25 °C; pulsed; tp ≤ 10 µs; Figure 3
-18
A
Ptot
total power dissipation
Tsp =25 °C; Figure 1
-
2.3
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−55
+150
°C
Source-drain diode
IS
source (diode forward) current (DC)
Tsp =25 °C-
2
A
ISM
peak source (diode forward) current Tsp =25 °C; pulsed; tp ≤ 10 µs-
7
A



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