© VITESSE SEMICONDUCTOR CORPORATION

Page 3

8/31/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7128

Hex Port Bypass Circuit / Dual Repeater

for 1.0625 Gb/s FC-AL Disk Arrays

G52177-0, Rev. 2.3

AC Characteristics

Figure 1: AC Timing Diagrams

Parameters

Description

Min.

Max.

Units

Conditions

Differential Inputs/Outputs

Latency from IN, LSI to LSO,

OUT

0.25

7.0

ns

75 Ohm Load

Differential Output Rise/Fall time

—

300

ps

Between 20% and 80%

Tested on a sample basis

Reference Clock Requirements

REFCLK input rise/fall times

—

2.0

ns

F

REFCLK Frequency

105

52.5

108

54

MHz

106.25 MHz Nominal if RFSEL is

HIGH

53.125 MHz Nominal if RFSEL is

LOW

T

REFCLK Period

9.2

18.5

9.53

19.0

ns

RFSEL = HIGH

RFSEL = LOW

Frequency Offset

-200

+200

ppm

Maximum frequency offset between

10 or 20 times REFCLK and the data

rate of the serial input to the CRU.

DC

REFCLK Duty Cycle

35

65

%

Measured at 1.5V

REFCLK Input HIGH/LOW time

2.5

—

ns.

INx+/-,

LSIx+/-

LSOx+/-,

OUTx+/-

REFCLK

T

80%

20%