| поискавой системы для электроныых деталей |
|
LP5550 датащи(PDF) 23 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
LP5550 датащи(HTML) 23 Page - National Semiconductor (TI) |
|
23 / 25 page ![]() Application Information (Continued) OUTPUT CAPACITOR The switching converter in the LP5550 is designed to be used with a 10uF ceramic output capacitor. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. The output capacitor of the switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the ca- pacitor can be dominated by capacitive, resistive, or induc- tive elements within the capacitor, depending on the fre- quency of the ripple current. Ceramic capacitors are predominately used in portable systems and have very low ESR and remain capacitive up to high frequencies. The switcher peak - to - peak output voltage ripple in steady state can be calculated as: LDO INFORMATION The LDOs included in the LP5550 provide static supply voltages for various functions in the processor. Use the following sections to determine loading and external compo- nents. LDO LOADING CAPABILITY The LDOs in the LP5550 can regulate to a variety of output voltages, depending on the need of the processor. These voltages can be programmed through the PWI. Table 1 summarizes the parameters of the LP5550 LDOs. TABLE 1. LDO Parameters PWI Register Output voltage range Recommended Maximum Output Current Dropout Voltage (typical) Typical Load LDO1 R8 0.6 V – 2.2 V 100 mA 200 mV PLL LDO2 R7 1.5 V – 3.3 V 250 mA 150 mV I/O LDO3 R2 V OSW + 0.05 V 1 0.7 V – 1.35 V 2 50 mA 200 mV Memory/Memory retention 1. LDO3 tracks the switching converter output voltage (V OSW) plus a 50 mV offset when the LP5550 is in active state. 2. LDO3 regulates at the set memory retention voltage when the LP5550 is in shutdown state. LDO OUTPUT CAPACITOR The output capacitor sets a low frequency pole and a high frequency zero in the control loop of an LDO. The capaci- tance and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requirements. The LDOs in the LP5550 are designed to be used with ceramic output capacitors. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. Use the following table to choose a suitable output capacitor: TABLE 2. Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) ESR range LDO1 1 µF – 20 µF (2.2 µF) 5 mohm – 500 mohm LDO2 2 µF – 20 µF (4.7 µF) 5 mohm – 500 mohm LDO3 0.7 µF – 2.2 µF (1.0 µF) 5 mohm– 500 mohm www.national.com 23 |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |