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HD49335F датащи(PDF) 14 Page - Renesas Technology Corp |
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HD49335F датащи(HTML) 14 Page - Renesas Technology Corp |
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14 / 30 page ![]() HD49335F/HF Rev.1.0, Feb.25.2004, page 14 of 29 Absolute Maximum Ratings (Ta = 25 °C) Item Symbol Ratings Unit Power supply voltage VDD 4.1 V Analog input voltage VIN –0.3 to AVDD +0.3 V Digital input voltage VI –0.3 to DVDD +0.3 V Operating temperature range Ta –20 to +85 °C Power dissipation Pt 590 mW Storage temperature Tstg –55 to +125 °C Power supply voltage Vopr 2.70 to 3.30 V Note: AVDD, AVSS are analog power source systems of CDS, PGA, and ADC. DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC. DVDD2, DVSS2 are buffer power source systems of ADC output. DVDD3, DVSS3 are general digital power source systems of TG. DVDD4, DVSS4 are buffer power source systems of H1 and H2. • Pin 2 multi bonds the DV SS1 and DVSS2 • When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output When Hi, pin 41 = Vgate input, pin 39 = ADCK input Electrical Characteristics (Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ) • Items Common to CDSIN and ADCIN Input Modes Item Symbol Min Typ Max Unit Test Conditions Remarks Power supply voltage range VDD 2.70 3.00 3.30 V fCLK hi 20 — 36 MHz LoPwr = low * 2 HD49335HF Conversion frequency fCLK low 5.5 — 25 MHz LoPwr = high * 2 HD49335F VIH2 DVDD 3.0 2.25 × — DVDD V Digital input voltage VIL2 0 — DVDD 3.0 0.6 × V CS, SCK, SDATA VOH DVDD –0.5 — — V IOH = –1 mA Digital output voltage VOL — — 0.5 V IOL = +1 mA IIH — — 50 µA VIH = 3.0 V Digital input current IIL –50 — — µA VIL = 0 V ADC resolution RES 10 10 10 bit ADC integral linearity INL — (2) — LSBp-p fCLK = 25 MHz ADC differential linearity+ DNL+ — 0.3 0.99 LSB fCLK = 25 MHz *1 ADC differential linearity– DNL– –0.99 –0.3 — LSB fCLK = 25 MHz *1 Sleep current ISLP –100 0 100 µA Digital input pin is set to 0 V, output pin is open Standby current ISTBY — 3 5 mA Digital I/O pin is set to 0 V Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes. 2. 2 divided mode: fCLK = 1/2CLK_in 3 divided mode: fCLK = 1/3CLK_in 3. Values within parentheses ( ) are for reference. |
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