84321AY

www.icst.com/products/hiperclocks.html

REV. B JUNE 9, 2005

10

Integrated

Circuit

Systems, Inc.

ICS84321

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

V

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 2A and 2B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

The ICS84321 has been characterized with 18pF parallel reso-

nant crystals.The capacitor values shown in

Figure 3 below were

determined using a 25MHz, 18pF parallel resonant crystal and

were chosen to minimize the ppm error. These same capacitor

values will tune any 18pF parallel resonant crystal over the fre-

quency range of 14MHz to 40MHz providing the other param-

eters specified in

Table 6, Crystal Characteristics, are satisfied.

C1

18p

X1

18pF Parallel Crystal

C2

22p

XTAL_IN

XTAL_OUT