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LPC47M14X датащи(PDF) 147 Page - SMSC Corporation

номер детали LPC47M14X
подробное описание детали  128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
PDF  205 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M14X датащи(HTML) 147 Page - SMSC Corporation

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SMSC DS – LPC47M14X
Page 147
Rev. 03/19/2001
NAME
REG OFFSET
(hex)
DESCRIPTION
GP5
Default = 0x00
on VTR POR
Bit 3 is reset on VCC
POR, Hard Reset
and VTR POR
4F
(R/W)
General Purpose I/0 Data Register 5
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
GP6
Default = 0x00
on VTR POR
50
(R/W)
General Purpose I/0 Data Register 6
Bit[0] GP60
Bit[1] GP61
Bit[7:2] Reserved
N/A
51
(R)
Reserved – reads return 0
N/A
52
(R)
Reserved – reads return 0
N/A
53
(R)
Reserved – reads return 0
INT_GEN1
Default = 0xFF
on VCC POR and
HARD RESET
54
(R/W)
Interrupt Generating Register 1 (Note 8)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Bit[0] Reserved
Bit[1] nINT1
Bit[2] nINT2
Bit[3] nINT3
Bit[4] nINT4
Bit[5] nINT5
Bit[6] nINT6
Bit[7] nINT7
Note:
To enable/disable this register see Logical
Device A (0xF1)
INT_GEN2
Default = 0xFF
on VCC POR and
HARD RESET
55
(R/W)
Interrupt Generating Register 2 (Note 8)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Bit[0] nINT8
Bit[1] nINT9
Bit[2] nINT10
Bit[3] nINT11
Bit[4] nINT12
Bit[5] nINT13
Bit[6] nINT14
Bit[7] nINT15
Note:
To enable/disable this register see Logical
Device A (0xF1)



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