LPC47M14X datasheet(143/205 Pages) SMSC

143 / 205 page

SMSC DS – LPC47M14X

Page 143

Rev. 03/19/2001

NAME

REG OFFSET

(hex)

DESCRIPTION

GP42

Default =0x01

on VTR POR

(R/W)

General Purpose I/0 bit 4.2

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[2] Alternate Function Select

1=nIO_PME

Note: configuring this pin function as output with non-

inverted polarity will give an active low output signal. The

output type can be either open drain or push-pull.

0=Basic GPIO function

Bits[6:3] Reserved

Bit[7] Output Type Select

1=Open Drain

0=Push Pull

GP43

Default = 0x01

on VTR POR

Bits[3:2] are reset

(cleared) on VCC

POR, VTR POR and

Hard Reset

(R/W)

General Purpose I/0 bit 4.3

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[3:2] Alternate Function Select

11=Either Edge Triggered Interrupt Input 3 (Note 1)

10=Reserved01=Device Disable Register Control. The

GP43 pin is an input, with non-inverted polarity. When

bits[3:2]=01, they cannot be changed by writing to these

bits; they are cleared by VCC POR, Hard Reset and VTR

POR. That is, when the DDRC function is selected for this

pin, it cannot be changed, except by a VCC POR, Hard

Reset or VTR POR.

The Device Disable register is controlled by the value of

the GP43 pin as follows:

If the GP43 pin is high, the Device Disable Register is

Read-Only.

If the GP43 pin is low, the Device Disable Register is

Read/Write.

00=Basic GPIO function

Bits[6:4] Reserved

Bit[7] Output Type Select

1=Open Drain

0=Push Pull

GP50

Default = 0x01

on VTR POR

(R/W)

General Purpose I/0 bit 5.0

Bit[0] In/Out : =1 Input, =0 Output

Bit[1] Polarity : =1 Invert, =0 No Invert

Bit[3:2] Alternate Function Select

11=Reserved

10=Reserved

01=nRI2 (Note 9)

00=GPIO

Bits[6:4] Reserved

Bit[7] Output Type Select

1=Open Drain

0=Push Pull

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