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LPC47M14X датащи(PDF) 121 Page - SMSC Corporation |
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LPC47M14X датащи(HTML) 121 Page - SMSC Corporation |
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121 / 205 page ![]() SMSC DS – LPC47M14X Page 121 Rev. 03/19/2001 A representation of the logic for the fan tachometer implementation is shown below. The following tables show examples of the desired functionality. Counts are based on 2 pulses per revolution tachometer outputs with a default divisor of 2. RPM TIME PER REVOLUTION TERM 1 FOR “DIVIDE BY 2” (DEFAULT) IN DECIMAL PRELOAD COUNT = (TERM 1) + PRELOAD COMMENTS 4400 13.64 ms 112 counts 32 144 Typical RPM 3080 19.48 ms 160 counts 32 192 70% RPM 2640 22.73 ms 186 counts 32 218 60% RPM 2204 27.22 ms 223 counts 32 255 (maximum count) 50% RPM MODE SELECT NOMINAL RPM TIME PER REVOLUTION PRELOAD COUNTS FOR THE GIVEN SPEED IN DECIMAL 70% RPM TIME PER REVOLUTION FOR 70% RPM Divide by 1 8800 6.82 ms 32 144 6160 9.74 ms Divide by 2 4400 13.64 ms 32 144 3080 19.48 ms Divide by 4 2200 27.27 ms 32 144 1540 38.96 ms Divide by 8 1100 54.54 ms 32 144 770 77.92 ms Pins 51 and 52 are the fan tachometer inputs, FAN_TACH2 and FAN_TACH1, respectively. The configuration registers for the fan tachometer inputs are defined in the “Runtime Registers” section. Programmable Divider 1, 2, 4, 8 Counter Preload Latch on Read Sync To nPME Logic 32 kHz MSB |
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