LPC47M14X datasheet(114/205 Pages) SMSC

114 / 205 page

SMSC DS – LPC47M14X

Page 114

Rev. 03/19/2001

The following GPIOs have “either edge triggered interrupt” (EETI) input capability. These GPIOs can generate a

PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in

the MSC_STS status register that is set on both edges. The corresponding bits in the PME and SMI status registers

are also set on both edges.

GP21, GP22

GP41, GP43

GP60, GP61

The following table summarizes the PME and SMI functionality for each GPIO.

It also shows the Either Edge

Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.

GPIO

PME

SMI

EETI

BUFFER

POWER

NOTES

GP10-GP17

Yes

VCC

GP20-GP22, GP24-GP26

Yes

GP21, GP22

VCC

GP27

Yes

nIO_SMI

VCC

GP30, GP31

Yes

VCC

GP32, GP33

Yes

VCC

GP35

VTR

GP36, GP37

VCC

GP40

VCC

GP41

Yes

VCC

GP42

nIO_PME

Yes

VTR

GP43

Yes

VCC

4, 6

GP50-GP52

Yes

VCC

GP53

Yes

VTR

1, 5

GP54-GP57

Yes

VCC

GP60, GP61

Yes

VTR

3, 4

Note 1: GP35 and GP53 have the IRTX function and their output buffers are powered by VTR so that the

pins are always forced low when not used.

Note 2: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These

pins are not used for wakeup.

Note 3: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is

Note 4: These pins can be used for wakeup events to generate a PME while the part is under VTR power

(VCC=0).

Note 5: These pins cannot be used for wakeup events to generate a PME while the part is under VTR power

(VCC=0). The GP32, GP33 and GP53 pins come up as output and low on a VCC POR and hard reset.

Also, GP32 and GP33

pins revert to their non-inverting GPIO input function when VCC is removed from the

part.

Note 6: GP43 defaults to the GPIO function on VCC POR and Hard Reset.

6.14.6

Either Edge Triggered Interrupts

Six GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-low

and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.

The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then

the bits that control input/output, polarity and open collector/push-pull have no effect on the function of the pin.

However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22).

A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function

is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are

cleared on a write of ‘1’. There are also status bits for the EETIs located in the MSC_STS register, which are also

cleared on a write of ‘1’. The MSC_STS register provides the status of all of the EETI interrupts within one register.

The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is

selected for the pin.

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