Pad Assignment

* The IC substrate should be connected to VDD in the PCB layout artwork.

Pad Coordinates

Unit: mil

Pad No.

X

Y

Pad No.

X

Y

Pad No.

X

Y

1

-57.91

45.52

19

-10.25

-61.96

37

58.10

28.84

2

-57.91

38.59

20

2.76

-61.96

38

58.10

36.19

3

-57.91

31.67

21

11.94

-62.50

39

58.10

43.53

4

-57.91

24.79

22

32.97

-62.50

40

58.10

50.87

5

-57.37

16.98

23

39.86

-62.50

41

58.10

58.22

6

-57.37

2.91

24

46.74

-62.50

42

37.26

63.04

7

-57.91

-8.60

25

58.10

-62.46

43

29.91

63.04

8

-57.91

-15.53

26

58.10

-55.04

44

22.57

63.04

9

-57.91

-22.49

27

58.10

-48.16

45

15.23

63.04

10

-57.91

-29.38

28

58.10

-36.30

46

7.88

63.04

11

-57.91

-36.26

29

58.10

-28.95

47

0.54

63.04

12

-57.91

-45.82

30

58.10

-21.61

48

-6.81

63.04

13

-57.91

-54.20

31

58.10

-15.22

49

-14.15

63.04

14

-57.91

-62.50

32

58.10

-7.88

50

-21.50

63.04

15

-47.20

-62.50

33

58.10

-0.54

51

-28.84

63.04

16

-33.43

-62.50

34

58.10

6.81

52

-36.18

63.04

17

-22.80

-62.46

35

58.10

14.15

53

-43.53

63.04

18

-16.37

-62.50

36

58.10

21.50

54

-50.87

63.04

HT1613C

Rev. 1.10

2

August 17, 2001

1

28

2

29

3

30

4

31

5

32

6

33

7

34

8

35

9

36

10

37

11

38

12

39

13

40

14

41

15

42

16

43

17

44

18

45

19

46

20

47

21

48

22

49

23

50

24

51

25

52

26

53

27

54

(0 , 0 )

RT

SE G 1 4

SE G 1 3

SE G 1 2

SE G 1 1

SE G 1 0

SE G 9

SE G 8

SE G 7

SE G 6

SE G 5

SE G 4

SE G 3

SE G 2

SE G 1

CO M 3

CO M 1

12/ 2 4

SE G 2 8

SE G 2 9

SE G 3 0

CO M 2

S2

X2

X1

TI M E R

S1

HK

IN T

T1

T2