LM32019CFW datasheet(13/14 Pages) TOPWAY

13 / 14 page

TOPWAY

LCD Module User Manual

LM32019CFW

URL:

www.topwaydisplay.com

www.topwaysz.com

Document Name: LM32019CFW-Manual-Rev0.4.DOC

Page: 13 of 14

(HEX)

R/W

Reset

Value

Descriptions

F500

Read /

Write

Bit[7:4] =

1110

Bit[3:0] =

1110

CS0 Configuration Port – Pulse Width

Bit[7:4] : Write Cycle Pulse Width

0000: 1 memory clock (24 MHz -> 41.6ns)

0001: 2 memory clocks

…………………………………………….

1110:15 memory clocks

1111: Reserved

Bit[3:0] : Read Cycle Pulse Width

0000: 1 memory clock (24 MHz -> 41.6ns)

0001: 2 memory clocks

……………………………………………

1110:15 memory clocks

1111: Reserved

F501

Read /

Write

0000 0000

CS0 Configuration Port – Control

Bit[7] : Enable bit

0:Disable CS0

1:Enable CS0

Bit[6] : Memory data bus width

0: 8-bit memory data bus width

1: 16-bit memory data bus width

Bit[5] : 16-bit SRAM option

0:two 8-bit SRAMs

1:one 16-bit SRAM

Bit[4] : Reserved

Bit[3] : CS0 assertion time relative to address assertion.

0:CS0 and address assert at the same time

1:CS0 lags address by 1 memory clock.

Bit[2] : CS0 Negation Timing

0:CS0 and Address negate at the same time

1:CS0 leads Address by 1 memory clock in write access.

Bit[1] : Write Enable Assertion Time

0: Write Enable and Address Assert at the same time.

1: Write Enable lags Address by 1 memory clock.

Bit[0] : Write Enable Negation Time

0: Write Enable and Address negate at the same time.

1: Write Enable leads Address by 1 memory clock.

F504

Read /

Write

Bit[3:0] =

1110

CS1 Configuration Port – Pulse Width

Bit[7:4] : Reserved

Bit[3:0] : Read Cycle Pulse Width

0000: 1 memory clock (24 MHz -> 41.6ns)

0001: 2 memory clocks

0001: 3 memory clocks

………………………………………………

1101:14 memory clocks

1110:15 memory clocks

1111: Reserved

F505

Read /

Write

0000 0000

CS1 Configuration Port – Control

Bit[7] : Enable bit

0:Disable CS1

1:Enable CS1

Bit[6] : Memory data bus width

0: 8-bit memory data bus width

1: 16-bit memory data bus width

Bit[5] : Reserved

Bit[4] : Reserved

Bit[3] : CS1 assertion time relative to address assertion.

0:CS1 and Address assert at the same time

1:CS1 lags Address by 1 memory clock.

Bit[2] : CS1 Negation Timing

0:CS1 and Address negate at the same time

1:CS1 leads Address by 1 memory clock in write access.

Bit[1:0] : Reserved

F6C4

Read /

Write

Bit[5:0] =

11 0011

Set Memory Clock Divide

Bit[7:6] = Reserved

Bit[5:0] = 010000 to set 24MHz memory clock for proper operations

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