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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HPC-DEV-ISE2 датащи(PDF) 11 Page - National Semiconductor (TI) |
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HPC-DEV-ISE2 датащи(HTML) 11 Page - National Semiconductor (TI) |
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11 / 30 page  Pin Descriptions (Continued) POWER SUPPLIES VCC1 VCC2 Positive Power Supply (two pins) GND Ground for On-Chip Logic DGND Ground for Output Buffers Note There are multiple electrically connected VCC pins on the chip GND and DGND are electrically isolated All VCC pins and all ground pins must be used CLOCK PINS CKI The System Clock Input CKO The System Clock Output (Inversion of CKI) Pins CKI and CKO are usually connected across an external crystal CK2 Clock Output (CKI divided by 2) OTHER PINS WO This is an active low open drain output which signals an illegal situation has been detected by the WATCHDOG logic ST1 Bus Cycle Status Output indicates first op- code fetch ST2 Bus Cycle Status Output indicates machine states (skip and interrupt) RESET Active low input that forces the chip to restart and sets the ports in a TRI-STATE mode RDYHLD Has two uses selected by a software bit This pin is either a READY input to extend the bus cycle for slower memories or a HOLD-REQUEST input to put the bus in a high impedance state for external DMA pur- poses In the second case the I4 pin can be- come the READY input Connection Diagrams Plastic and Leaded Chip Carriers TLDD10422 – 18 Top View See NS Package Number V68A 11 |
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