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OPA207

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SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019

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Copyright © 2017–2019, Texas Instruments Incorporated

9 Power Supply Recommendations

The OPA207 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from

–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 36 V can permanently damage the device; see the

Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout

Guidelines.

10 Layout

10.1 Layout Guidelines

The OPA207 series has low offset voltage and drift. To achieve highest performance, optimize the circuit layout

and mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the op

amp inputs. Connections of dissimilar metals generate thermal potential, which can degrade the ultimate

performance of the OPA207. These thermal potentials can be made to cancel by assuring that they are equal in

both input terminals.

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Keep the thermal mass of the connections to the two input terminals similar.

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Locate heat sources as far as possible from the critical input circuitry.

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Shield operational amplifier and input circuitry from air currents, such as cooling fans.

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to

the analog circuitry.

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Connect low-ESR, 0.1–µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

•

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close as possible to the device. As shown in Layout Example, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

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Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

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For best performance, TI recommends cleaning the PCB following board assembly.

•

Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to

remove moisture introduced into the device packaging during the cleaning process. A low temperature, post-

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.