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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32MP157C датащи(PDF) 237 Page - STMicroelectronics |
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STM32MP157C датащи(HTML) 237 Page - STMicroelectronics |
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237 / 258 page  DS12505 Rev 2 237/258 STM32MP157C Electrical characteristics 238 6.3.40 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 115 and Table 116 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 13: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 0x10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5×VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. IDDA1V8_DSI(PHY) Power down - - 1 - µA High-Speed TX 2 lanes in High-Speed mode - 400 - LPDT transmit All data lanes in LPDT mode - 1 - LPDT receive All data lanes in LPDT mode - 1 - 1. Guaranteed by design unless otherwise specified. Table 114. DSI PHY characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Table 115. Dynamics characteristics: JTAG characteristics Symbol Parameter Conditions Min Typ Max Unit Fpp TCK clock frequency 2.7 V < VDD < 3.6 V - - 35 MHz 1/tc(TCK) 1.71 V < VDD< 3.6 V - - 27 tisu(TMS) TMS input setup time -2.5 - - tih(TMS) TMS input hold time -1 - - tisu(TDI) TDI input setup time -2 - - tih(TDI) TDI input hold time -1 - - tov (TDO) TDO output valid time 2.7 V <VDD< 3.6 V - 8 14 1.71 V <VDD< 3.6 V - 8 18 toh(TDO) TDO output hold time -7 - - |
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