EMC1822 datasheet(33/103 Pages) MICROCHIP

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System Management Bus Protocol

The EMC1822/23/24/25/43 devices communicate with a host controller through the SMBus/I2C. The

SMBus/I2C is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 3-1. Stretching of the SMCLK signal is supported;

however, the EMC1822/23/24/25/43 devices do not stretch the clock signal.

8.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus/I2C data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus/I2C clock line is in a logic ‘1’ state.

8.2

SMBus Address and RD/WR Bit

The SMBus address byte consists of the 7-bit client address followed by the RD/WR indicator bit. If this

RD/WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD/WR bit is a logic ‘1’,

the SMBus Host is reading data from the client device.

The response to the slave address 1001_100xb for -1 parts and 1001_101xb for -2 parts.

8.3

SMBus Data Bytes

All SMBus data bytes are sent Most Significant bit first and are composed of 8 bits of information.

8.4

SMBus ACK and NACK Bits

The SMBus client acknowledges all data bytes that it receives. This is done by the client device pulling

the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write

Byte and Block Write protocols.

The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the

SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK

(acknowledge) each data byte that it receives, except the last data byte.

8.5

SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’

state while the SMBus clock line is in a logic ‘1’ state. When a EMC1822/23/24/25/43 device detects an

SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface

and prepare to receive further communications.

8.6

SMBus Time-Out

The EMC1822/23/24/25/43 device family includes an SMBus time-out feature. Following a 30 ms period

of inactivity on the SMBus where the SMCLK pin is held low, the device will time-out and reset the SMBus

interface.

The time-out function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the

Consecutive Alert register (see Consecutive Alert Register (address 22h)).

Multi-Channel Low Voltage Temp Sens...

System Management Bus Protocol

Datasheet

DS20006048A-page 33

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