FC9961

2015. 03. 23

3/7

Revision No : 1

Sym

Description

Min

Typ

Max

Units Conditions

Internal Regulator

V

DD

Internally regulated voltage

-

7.25

7.50

7.75

V

V

500pF at GATE; R

ΔV

DD, line

Line regulation of V

DD

-

0

-

1.0

V

V

500pF at GATE; R

ΔV

DD, load

Load regulation of V

DD

-

0

-

100

mV

I

500pF at GATE; R

UVLO

V

threshold

*

6.45

6.70

6.95

V

V

∆UVLO

V

hysteresis

-

-

500

-

mV

V

I

IN,MAX

Maximum input current

(limited by UVLO)

#

3.5

-

-

mA

V

O

C

#

1.5

-

-

V

O

C

PWM Dimming

V

EN(lo)

PWMD input low voltage

*

-

-

0.8

V

V

V

EN(hi)

PWMD input high voltage

*

2.0

-

-

V

V

R

EN

Internal pull-down resistance

at PWMD

-

50

100

150

kΩ

V

Average Current Sense Logic

V

CS

Current sense reference voltage -

238

250

262

mV

---

A

V(LD)

LD-to-CS voltage ratio

-

0.176 0.181 0.187

-

---

AV

LD(OFFSET)

LD-to-CS voltage offset

-

0

-

10

mV

Offset = V

V

-

CS threshold temp regulation

*

-

-

5.0

mV

---

V

LD(OFF)

LD input voltage, shutdown

-

-

150

-

mV

V

ΔV

LD(OFF)

LD input voltage, enable

-

-

200

-

mV

V

T

BLANK

Current sense blanking interval

*

150

-

280

ns

---

T

ON(min)

Minimum on-time

-

-

-

1000

ns

CS = V

D

MAX

Maximum steady-state duty

cycle

-

75

-

-

%

Reduction in output LED current

may occur beyond this duty cycle

Short Circuit Protection

V

CS

Hiccup threshold voltage

-

410

-

470

mV

---

T

DELAY

Current limit delay CS-to-GATE

-

-

-

150

ns

CS = V

T

HICCUP

Short circuit hiccup time

-

350

-

460

μs

---

T

ON(min)

Minimum on-time (short circuit)

-

-

-

430

ns

CS = V

DD

Notes:

*

Denotes the specifications which apply over the full operating ambient temperature range of -40°C < T

#

Guaranteed by design.