FC9931 datasheet(2/6 Pages) FS

2 / 6 page

FC9931

2012. 10. 31

2/6

Revision No : 0

Absolute Maximum Ratings

VIN to GND ------------------------------------------------------------------- -0.5V to +470V

VDDto GND

-0.3V to +13,5V

CS1, CS2, PWM_D, GATE, RT to GND

-0.3V to (VDD + 0.3V)

Operating Temperature Range

-40°C to +85°C

Junction Temperature

Storage Temperature Range

-65°C to +150°C

Continuous Power Dissipation (Ta=+25°C) (Note 1)

16-Pin SO (derate 7.5mW/°C above +25°C)

8-Pin DIP (derate 9mW/°C above +25°C)

8-Pin SO (derate 6.3mW/°C above +25°C)

Stresses beyond those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions

beyond those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note1: Also limited by package power dissipation limit, whichever is lower.

Electrical Characteristics (cont.) (The * denotes the specifications which apply over the full operating juction

temperature range of -40°C < T < +85°C, otherwise the specifications are at T = 25°C, VIN= 12V, unless otherwise noted)

Symbol Description

Min Typ Max Units Conditions

Input

VINDC Input DC supply voltage range*

8.0

450

DC input voltage

IINSD

Shut-Down mode supply current*

0.5

mA Pin PWM_D to GND

Internal Regulator

VDD

Internally regulated voltage

7.12

7.5 7.88

VIN = 8V, IDD(ext)=0,

GATE = 500pF, RT = 226KΩ

ΔVDD,line Line regulation of VDD

1.0

V VIN = 8 - 450V, IDD(ext) = 0,

GATE = 500pF, RT = 226kΩ

UVLO VDD undervoltage lockout

threshold

6.45

6.7 6.95

VIN rising

ΔUVLO VDD undervoltage lockout

hysteresis

500

mV ---

PWM Dimming

VPWMD(lo) PWM_D input low voltage

1.0

VIN = 8-450V

VPWMD(hi) PWM_D input high voltage

2.4

VIN = 8-450V

RPWMD PWM_D pull-down resistance

100 150

kΩ

VPWMD = 5V

GATE

VGATE(hi) GATE high output voltage*

VDD-

0.3

VDD

IGATE = -10 mA, VDD = 7.5V, VIN open

VGATE(lo) GATE low output voltage

0.3

IGATE = 10 mA VDD = 7.5V, VIN open

TRISE

GATE output rise time

ns CGATE = 500рF, VDD = 7.5V, VIN open

TFALL GATE output fall time

ns CGATE = 500pF, VDD = 7.5V, VIN open

TDELAY Delay from CS trip to GATE

150 300

ns VCS1, VCS2 = -100mV

TBLANK Blanking delay

150

215 280

ns VCS1, VCS2 = -100mV

Oscillator

FOSC

Oscillator frequency

100 120 kHz RT = 226 kΩ

Comparators

TOFFSET1

TOFFSET2 Comparator input offset voltage*

-15

mV ---

-------------------------------------------------------------------

-------------------------------

+125°C

-------------------------------

750mW

900mW

630mW

-------------------------------

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