LTC6900

8

6900f

SUPPLY VOLTAGE (V)

2.5

–0.05

0

0.05

0.10

0.15

3.0

3.5

4.0

4.5

6900 F05

5.0

5.5

85

°C

–40

°C

25

°C

PIN 4 = FLOATING (

÷10)

Figure 5. Supply Sensitivity

TIME AFTER POWER APPLIED (

µs)

0

20

30

40

600

400k

1000

6900 F06

10

0

–10

200

400

800

50

60

70

63.2k

20k

POWER SUPPLY REJECTION

Low Frequency Supply Rejection (Voltage Coefficient)

Figure 5 shows the output frequency sensitivity to power

supply voltage at several different temperatures. The

LTC6900 has a guaranteed voltage coefficient of 0.1%/V

but, as Figure 5 shows, the typical supply sensitivity is

twice as low.

High Frequency Power Supply Rejection

The accuracy of the LTC6900 may be affected when its

power supply generates significant noise with a frequency

a switching power supply is used to power the LTC6900,

and if the ripple of the power supply is more than 20mV,

make sure the switching frequency and its harmonics are

not related to the output frequency of the LTC6900.

Otherwise, the oscillator may show additional frequency

error.

If the LTC6900 is powered by a switching regulator and the

switching frequency or its harmonics coincide with the

output frequency of the LTC6900, the jitter of the oscillator

output may be affected. This phenomenon will become

noticeable if the switching regulator exhibits ripples be-

yond 30mV.

START-UP TIME

The start-up time and settling time to within 1% of the final

10

independent from the setting of the divider pin. For in-

of its 200kHz final value (N = 10) in approximately 380

µs.

Figure 7 shows an application where a second set resistor

switch S1. When switch S1 is open, the output frequency

When switch S1 is closed, the output frequency of the

LTC6900 depends on the value of the parallel combination

The start-up time and settling time of the LTC6900 with

above. Once the LTC6900 starts and settles, and switch S1

closes (or opens), the LTC6900 will settle to its new output

frequency within approximately 70

µs.

Jitter

The Peak-to-Peak Jitter vs Output Frequency graph, in the

Typical Performance Characteristics section, shows the

typical clock jitter as a function of oscillator frequency and

power supply voltage. The capacitance from the SET pin,

(Pin 3), to ground must be less than 10pF. If this require-

ment is not met, the jitter will increase.

Figure 6. Start-Up Time

APPLICATIO S I FOR ATIO