MIC4609 datasheet(16/34 Pages) MICROCHIP

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MIC4609

DS20005531A-page 16

 2016 Microchip Technology Inc.

4.0

FUNCTIONAL DESCRIPTION

The MIC4609 is a noninverting, 600V three-phase

IGBT/MOSFET driver designed to independently drive

six IGBTs or MOSFETs in a three-phase bridge. The

MIC4609 offers a wide 10V-to-20V VDD operating

supply range with six independent inputs (TTL or

3.3V CMOS compatible).

The driver is comprised of six input buffers with

hysteresis, four independent UVLO circuits (three

high-side monitoring the HB voltage and one low-side

monitoring the VDD voltage), and six output drivers.

The high-side output drivers utilize a high-speed

level-shifting circuit that is referenced to the HS pin. An

overcurrent protection circuit turns off all outputs during

an overcurrent fault.

4.1

UVLO Protection

The UVLO circuits force the driver's outputs low until

the supply voltage exceeds the UVLO threshold.

Hysteresis in the UVLO circuits prevents system noise

and finite circuit impedance from causing chatter during

turn-on.

The UVLO circuits are illustrated in the functional block

diagrams. The low-side UVLO circuit, Functional Block

Diagram MIC4609 – Phase x Drive Circuit, monitors

the voltage between the VDD and VSS pins. The circuit

keeps all the drivers off when VDD is less than the

UVLO threshold voltage.

The three high-side UVLO circuits, shown in Typical

Application Circuit MIC4609 – 300V, 3-Phase Motor

Driver, monitor the voltage between the xHB and xHS

pins. The circuit keeps its respective high-side output

off when VHB -VHS is less than the UVLO threshold

voltage.

4.2

Startup and UVLO

The startup sequence is illustrated in Figure 4-1. As

VDD rises above an unspecified threshold, VT, the

internal circuitry becomes active, the FAULT pin

asserts low and the UVLO circuitry begins to monitor

VDD. When the rising VDD reaches the UVLO

threshold, a current source begins charging the RCIN

pin's external capacitor until it reaches the RCIN delay

threshold. The output drivers are enabled once the

RCIN threshold is reached and the EN pin is asserted

high.

FIGURE 4-1:

Startup and Fault Timing Diagram.

VDD

UVLO Rising Level (VDDR)

FAULT

RCIN

UVLO Falling Level

RCIN Delay Threshold

UVLO

(Internal)

Normal Operation

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