LTC6903/LTC6904

9

69034fa

ACK

123

ADDRESS

456789

123456789

123456789

6903 TD03

0

0

101110

0

0

1011

ADR

WR

11111111

OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6

11111100

DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0

ACK

STOP

START

SDA

SCL

ACK

SDA

SCL

6903 TD02

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

Timing Diagram (LTC6904)

TI I G DIAGRA S

Typical LTC6904 Input Waveform—Programming Frequency to 68MHz (ADR Pin Set LOW)

Serial Port Register Description

OCT[3:0] - Frequency Divider Setting. (See Frequency

Setting Section)

DAC[9:0] - Master Oscillator Frequency Setting. (See

Frequency Setting Section)

CNF[1:0] - Output Configuration - This controls outputs

CLK and CLK according to Table 2.

LTC6903 SPI Compatible Interface

A serial data transfer is composed of sixteen (16) bits of

data labeled D15 through D0. D15 is the first bit of data

presented in each transaction. All serial port register bits

are set LOW on power-up.

APPLICATIO S I FOR ATIO

Writing Data (LTC6903 Only)

When the SEN line is brought LOW, serial data presented

on the SDI input is clocked in on the rising edges of SCK

until SEN is brought HIGH. On every eighth rising edge of

SCK, the preceding 8-bits of data are clocked into the

internal register. It is therefore possible to clock in only the

8 {D15 - D8} most significant bits of data rather than

completing an entire transfer.

The serial data transfer starts with the most significant bit

and ends with the least significant bit of the data, as shown

in the timing diagram.