Timing Specification

Symbol

Parameter

Min.

Typ.

Max.

Unit

Clock Parameters

Pixel Rate Clock

166

¾¾

ns

ADCCLK Pulse High Width

80

¾

ns

ADCCLK Pulse Low Width

80

¾

ns

CDSCLK1 Pulse Width

20

¾¾

ns

CDS Mode CDSCLK2 Pulse Width

20

¾¾

ns

SHA Mode CDSCLK2 Pulse Width

40

¾¾

ns

CDSCLK2 Falling to ADCCLK Falling

60

¾¾

ns

ADCCLK Falling to CDSCLK1 Rising

2

¾¾

ns

ADCCLK Falling to CDSCLK2 Rising

2

¾¾

ns

Analog Sampling Delay

5

¾¾

ns

Serial Interface

Maximum SCLK Frequency

10

¾¾

MHz

SLOAD to SCLK Setup Time

10

¾¾

ns

SCLK to SLOAD Hold Time

10

¾¾

ns

SDATA to SCLK Rising Setup Time

10

¾¾

ns

SCLK Rising to SDATA Hold Time

10

¾¾

ns

Falling to SDATA Valid

10

¾¾

ns

Data Output

Output Delay

¾

8

¾

ns

Latency (Pipeline Delay)

¾

9

¾

Cycles

HT82V36

Rev. 1.30

4

June 29, 2004

Functional Description

Integral Nonlinear (INL)

Integral nonlinear error refers to the deviation of each in-

dividual code from a line drawn from zero scale through

positive full scale. The point used as zero scale occurs 1

/2 LSB before the first code transition. Positive full scale

is defined as a level 1/2 LSB beyond the last code transi-

tion. The deviation is measured from the middle of each

particular code to the true straight line.

Differential Nonlinear (DNL)

An ideal ADC exhibits code transitions that are exactly 1

LSB apart. DNL is the deviation from this ideal value.

Thus every code must have a finite width. No missing

codes guaranteed to 16-bit resolution indicates that all

4096 codes, respectively, must be present over all oper-

ating ranges.

Offset Error

The first ADC code transition should occur at a level 1/2

LSB above the nominal zero scale voltage.

The offset error is the deviation of the actual first code

transition level from the ideal level.

Gain Error

The last code transition should occur for an analog

value 1/2 LSB below the nominal full-scale voltage.

Gain error is the deviation of the actual difference be-

tween first and last code transitions and the ideal differ-

ence between the first and last code transitions.

Aperture Delay

The aperture delay is the time delay that occurs when a

sampling edge is applied to the HT82V36 until the actual

sample of the input signal is held. Both CDSCLK1 and

CDSCLK2 sample the input signal during the transition

from high to low, so the aperture delay is measured from

each clock

¢s falling edge to the instant the actual inter-

nal sample is taken.