STR720 datasheet(28/401 Pages) STMICROELECTRONICS

28 / 401 page

STR720 - ARCHITECTURE OVERVIEW

28/401

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16 programmable priority levels for each interrupt channel mapped on IRQ

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hardware support for interrupt nesting (up to 16 interrupt requests can be nested), with

internal HW nesting stack

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at register offset 0x18h, the start address of the ISR of the highest priority interrupt or directly

the jump instruction to it (defined by the application).

The EIC performs the following operations without software intervention:

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reject/accept an interrupt request according to the related channel mask bit,

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compare all IRQ requests with the current priority level interrupt. The IRQ is asserted if the

priority of the current interrupt request is higher than the stored current priority,

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load the address vector of the highest priority IRQ to the Interrupt Vector Register (offset

0x18h)

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save the previous interrupt priority in the HW priority stack whenever a new IRQ is accepted

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update the Current Interrupt Priority Register with the new priority whenever a new interrupt

is accepted

5.1.1

IRQ Interrupt Vector Table

Up to 32 interrupt channels are mapped on low priority ARM720T interrupt request pin (IRQ).

Hereafter the mapping of the different interrupt sources on the vector tables is described. The

highest-priority interrupt request will be issued on ARM720T IRQ pin. In case of multiple

interrupt requests mapped on the same interrupt vector, a polling on interrupt flags contained

inside peripherals must be performed by the application code in order to establish the exact

source of interrupt (see Interrupt Flags column in Table 13 on page 32).

There are 16 priority levels for IRQ mapped interrupt. The internal daisy-chain will define the

priority relationship for different interrupt vectors having the same priority level: the higher is

the interrupt vector number the higher is the priority in the daisy chain.

Interrupt Vector 0

•

External interrupt requests.

Four different interrupt requests are OR-ed together to generate a single interrupt request:

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External interrupt 0 (EINT0)

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External interrupt 1 (EINT1)

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External interrupt 2 (EINT2)

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External interrupt 3 (EINT3)

Interrupt Vector 1

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External interrupt request 4 (EINT4).

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