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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STR720 датащи(PDF) 144 Page - STMicroelectronics |
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STR720 датащи(HTML) 144 Page - STMicroelectronics |
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144 / 401 page  STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 144/401 Bit 5:0 = MX[5:0]: PLL Multiplication Factor. This bit field selects the multiplier factor used to generate PLL output clock from its input reference clock. Refer to Table 37 for multiplier settings WARNING Not all clock selections are possible and setting the system clock to any unsupported frequency may cause the system to malfunction. In this case the only way to start again is a hardware reset. For the allowed values, refer to section 25 on page 364. 1 0 PLLCLKREF/4 1 1 PLLCLKREF/8 Table 37. PLL multiplication factors MX5 MX4 MX3 MX2 MX1 MX0 Multiply factor 0 to 7 N/A 000111 8 001000 9 001001 10 ... ... ... ... ... ... ... 001111 16 010000 17 ... ... ... ... ... ... ... 011111 32 100000 33 ... ... ... ... ... ... ... 111111 64 Table 36. PLL divider settings 1 |
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