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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STR720 датащи(PDF) 138 Page - STMicroelectronics |
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STR720 датащи(HTML) 138 Page - STMicroelectronics |
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138 / 401 page  STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 138/401 13 RESET AND CLOCK CONTROL UNIT (RCCU) 13.1 Introduction Reset and Clock Control Unit (RCCU) is responsible of the control and distribution of the reset and the clock signals of the STR720. 13.2 Main Features ■ Three reset inputs: Watchdog reset, Hardware reset and Software reset ■ Two clock inputs: CLK and CLK_AF ■ Three clock outputs: AHB clock (AHB_CLK), APB clock (APB_CLK) and ATAPI clock (ATAPI_CLK) ■ PLL control including: • PLL operation mode (POFF output) and multiplication/division (MX and DX Output) control • PLL reference (PLLREFCLK) clock selectable between CLK and CLK/2 ■ Four clock domains: • AHB clock can be: CLK clock, CLK clock divided by 2, 32, 64 CLK (or CLK/2) clock multiplied by the PLL External low frequency clock (CLK_AF, when available) • APB clock can be: AHB clock divided by 2, 4, 8, 16 • ATAPI clock can be: AHB clock divided by 2 AHB clock divided by 3 • PLLCKREF can be: CLK clock CLK clock divided by 2 ■ Four different operating modes: Run mode Idle mode Slow mode Stop mode ■ Low frequency clock (CLK_AF) selection for low power consumption modes. 1 |
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