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High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
9
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
READ CYCLE2 (1,3,4)
READ CYCLE3 (1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
OE
t
OHZ
(1,5)
t
OE
t
OLZ
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
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