201-0000-035 Rev 1.1, 5/8/2000
21
CHRONTEL
CH7009A
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in Figure 12.
.
Note: The acknowledge is from the CH7009 (slave).
Figure 12: Auto-Increment Write Cycle
During the auto-increment mode transfers, the register address pointer continues to increment for each write cycle
until AR[6:0] = 4F. The next byte of information represents a new auto-sequencing “Starting address”, which is the
address of the register to receive the next byte. The auto-sequencing then resumes based on this new “Starting
address”. The auto-increment sequence can be terminated any time by either a “STOP” or “RESTART” condition.
The write operation can be terminated with a “STOP” condition.
CH7009 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7009 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[6:0], containing the address of the register that the master device intends to read from in AR[6:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START”, without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). For alternating modes, another RESTART condition, followed by another DAB with R/W =
0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in Figure 13.
SD
SC
1 - 8
9
RAB n
ACK
Start
Stop
CH7009
acknowledge
1 - 8
Data n
9
1 - 8
9
ACK
Data n+1
ACK
CH7009
acknowledge
CH7009
acknowledge
CH7009
acknowledge
1 - 7
Device ID
8
R/W*
9
ACK
I2C
Condition
Condition
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