LAN9117 datasheet(39/131 Pages) SMSC

39 / 131 page

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

SMSC LAN9117

Revision 1.1 (05-17-05)

DATASHEET

Note 3.7

The host must do only read accesses prior to the ready bit being set.

Once the READY bit is set, the LAN9117 is ready to resume normal operation. At this time the WUPS

field can be cleared.

3.10.2.2

D2 Sleep

In this state, as shown in Table 3.9, all clocks to the MAC and host bus are disabled, and the PHY is

placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY

(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The

PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,

the LAN9117 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the

D2 state.

Note 3.8

If carrier is present when this state is entered detection will occur immediately.

If properly enabled via the ED_EN and PME_EN bits, LAN9117 will assert the PME hardware signal

upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b.

Note 3.9

The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the

setting of PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return LAN9117

to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required

to check the READY bit and verify that it is set before attempting any other reads or writes of the

device. Before LAN9117 is fully awake from this state the EDPWRDOWN bit in register 17 of the PHY

must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit until the

READY bit is set. After clearing the EDPWRDOWN bit the LAN9117 is ready to resume normal

operation. At this time the WUPS field can be cleared.

Table 3.9 Power Management States

LAN9117

BLOCK

(NORMAL OPERATION)

(WOL)

(ENERGY DETECT)

PHY

Full ON

Energy Detect Power-Down

MAC Power

Management

Full ON

RX Power Mgmt. Block

OFF

MAC and Host

Interface

Full ON

OFF

Internal Clock

Full ON

OFF

KEY

CLOCK ON

BLOCK DISABLED – CLOCK ON

FULL OFF

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