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High Speed CMOS Logic – 74HC05

Rev 1.0

22/04/19

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

4.5V

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Leakage

Current

6.0V

1

10

40

µA

Maximum Three-

State Leakage

Current

6.0V

Output in high

impedance state,

±0.5

±5

±10

µA

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

90

115

135

4.5V

18

23

27

Maximum Propagation

Delay, Input A or B to

Output Y

(Figure 1,2)

6.0V

Input

15

20

23

ns

2.0V

75

95

110

4.5V

15

19

22

Maximum Output

Transition Time,

Any Output

(Figure 1,2)

6.0V

Input

13

16

19

ns

 

LIMITS

5. Not production tested in die form, characterized by chip design and tested in package.

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Maximum Input

Capacitance

6.0V

-

10

10

10

pF

Maximum Three-State

Output Capacitance

6.0V

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance Per Buffer

6

5.0V

4

pF