LT3093 datasheet(21/32 Pages) AD

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LT3093

Rev. 0

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the LT3093. Magnetic coupling decreases rapidly with

increasing distance. If the switching regulator is placed

too far away (conservatively more than a couple inches)

from the LT3093, the lack of an input capacitor presents a

high impedance at the input of the LT3093 and oscillation

may occur. It is generally a common (and preferred) prac-

tice to bypass regulator inputs with some capacitance, so

this option is fairly limited in its scope and not the most

palatable solution.

To that end, ADI recommends referencing the LT3093

demo board layout for achieving the best possible PSRR

performance. Two main factors contribute to higher PSRR

with a poor layout. Parasitic trace inductance coupled with

the low ESR ceramic input capacitor can lead to higher

ripple at the input of the LDO than at the output of the

driving supply. Also, physical loops create magnetic fields

that couple from the input to the output. The LT3093

demo board utilizes layout techniques to minimize both

parasitic inductance in traces and coupling of magnetic

loops, preventing PSRR degradation while keeping the

input capacitor.

Filtering High Frequency Spikes

For applications where the LT3093 is used to post-regu-

late a switching converter, its high PSRR effectively sup-

presses any harmonic content present at the switching

frequency (typically 100kHz to 4MHz). However, there are

very high frequency (hundreds of MHz) spikes associated

with the switcher’s power switch transition times that are

beyond the LT3093’s bandwidth and will almost directly

pass through to the output. While the output capacitor is

partly intended to absorb these spikes, its ESL will limit

its ability at these frequencies. A ferrite bead or even the

inductance associated with a short (e.g. 0.5”) PCB trace

coupled with a capacitor with a low impedance at the

transition frequency can serve as an LC-filter to suppress

these very high frequency spikes.

Output Noise

The LT3093 offers many advantages with respect to noise

performance. Traditional linear regulators have several

sources of noise. The most critical noise sources for a tra-

ditional regulator are its voltage reference, error amplifier,

noise from the resistor divider network used for setting

output voltage and the noise gain created by this resistor

divider. Many low noise regulators pin out their voltage

reference to allow for noise reduction by bypassing the

reference voltage.

Unlike most linear regulators, the LT3093 does not use a

voltage reference; instead it uses a 100µA current refer-

ence. The current reference operates with typical noise

current level of 27pA/√Hz (8nARMS over the 10Hz to

100kHz bandwidth). The resultant voltage noise equals

the current noise multiplied by the resistor values, which

is then RMS summed with the error amplifier’s noise and

the resistor’s Johnson noise of √4kTR (k = Boltzmann’s

constant, 1.38 • 10–23 J/K, and T is absolute temperature)

to give the net output noise.

One problem faced by conventional linear regulators is

that the resistor divider setting the output voltage gains up

the reference noise. In contrast, the LT3093’s unity-gain

follower architecture presents no gain from the SET pin

to the output. Therefore, using a capacitor to bypass the

SET pin resistor allows output voltage noise to be inde-

pendent of the programmed output voltage. The resultant

output noise is then determined only by the error ampli-

fier’s noise, typically 2nV/√Hz from 1kHz to 1MHz and

0.8µVRMS in the 10Hz to 100kHz bandwidth when using

a 4.7µF SET pin capacitor. Paralleling multiple LT3093s

further reduces noise by √N for N parallel regulators.

Refer to the Typical Performance Characteristics sec-

tion for noise spectral density and RMS integrated

noise performance over various load currents and SET

pin capacitances.

SET Pin (Bypass) Capacitance: Noise, PSRR,

Transient Response and Soft-Start

In addition to reducing output noise, using a SET pin

bypass capacitor also improves PSRR and transient per-

formance. Note that any bypass capacitor leakage deterio-

rates the LT3093’s DC regulation. Capacitor leakage of as

little as 100nA causes a 0.1% DC error. ADI recommends

the use of a good quality low leakage ceramic capacitor.

Using a SET pin bypass capacitor also soft starts the

output and limits inrush current. The RC time constant

formed by the SET pin resistor and capacitor determines

APPLICATIONS INFORMATION

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