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ADP5072ACBZ-R7 датащи(PDF) 15 Page - Analog Devices

номер детали ADP5072ACBZ-R7
подробное описание детали  1 A/0.6 A DC to DC Switching Regulator Independent Positive and Negative Outputs
PDF  24 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADP5072ACBZ-R7 датащи(HTML) 15 Page - Analog Devices

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Data Sheet
ADP5072
Rev. 0 | Page 15 of 24
To configure the simultaneous enable mode, connect the SEQ pin
to the PVIN pin. Both regulators power up simultaneously
when the EN2 pin is taken high. The EN1 pin enable can be
used to enable the internal references ahead of enabling the
outputs, if desired. The simultaneous enable mode timing is
shown in Figure 41.
VIN
VPOS
TIME
VNEG
SIMULTANEOUS ENABLE MODE
(SEQ = HIGH, EN2 = HIGH)
Figure 41. Simultaneous Enable Mode
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the EN1 pin or EN2 pin. Keep the other pin low. The secondary
supply is enabled when the primary supply completes soft start and
its feedback voltage reaches approximately 85% of the target
value. The sequential enable mode timing is shown in Figure 42.
TIME
TIME
VPOS
VNEG
VPOS
VNEG
1. VPOS FOLLOWED BY VNEG
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
2. VNEG FOLLOWED BY VPOS
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
VIN
VIN
Figure 42. Sequential Enable Mode



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