AM186EM-33VCSLASHW datasheet(38/98 Pages) AMD

38 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINA R Y

Pseudo Static RAM (PSRAM) Support

The Am186EM and Am188EM microcontrollers sup-

port the use of PSRAM devices in low memory chip-se-

lect (LCS) space only. When PSRAM mode is enabled,

the timing for the LCS signal is modified by the chip-select

control unit to provide a CS precharge period during

PSRAM accesses. The 40-MHz timing of the Am186EM

and Am188EM microcontrollers is appropriate to allow

70-ns PSRAM to run with one wait state. PSRAM mode is

enabled through a bit in the Low Memory Chip-Select

(LMCS) Register. The PSRAM feature is disabled on CPU

reset.

In addition to the LCS timing changes for PSRAM pre-

charge, the PSRAM devices also require periodic refresh of

all internal row addresses to retain their data. Although re-

fresh of PSRAM can be accomplished several ways, the

Am186EM and Am188EM microcontrollers implement auto

refresh only.

The Am186EM and Am188EM microcontrollers gener-

ate RFSH, a refresh signal, to the PSRAM devices when

PSRAM mode is enabled. No refresh address is required

by the PSRAM when using the auto refresh mechanism.

The RFSH signal is multiplexed with the MCS3 signal pin.

When PSRAM mode is enabled, MCS3 is not available for

use as a chip-select signal.

The refresh control unit must be programmed before

accessing PSRAM in LCS space. The refresh counter

in the Clock Prescaler (CDRAM) Register must be con-

figured with the required refresh interval value. The

ending address of LCS space and the ready and wait-

state generation in the LMCS Register must also be

programmed. The refresh counter reload value in the

CDRAM Register should not be set to less than 18

(12h) in order to provide time for processor cycles

within refresh. The refresh address counter must be set

to 000000h to prevent another chip select from assert-

ing.

LCS is held High during a refresh cycle. The A bus is

not used during refresh cycles. The LMCS Register

must be configured to external ready ignored (R2=1)

with one wait state (R1–R0=01b), and the PSRAM

mode enable bit (SE) must be set.

PERIPHERAL CONTROL BLOCK (PCB)

The integrated peripherals of the Am186EM and

Am188EM microcontrollers are controlled by 16-bit

read/write registers. The peripheral registers are con-

tained within an internal 256-byte control block. The

registers are physically located in the peripheral de-

vices they control, but they are addressed as a single

256-byte block. Figure 7 shows a map of these regis-

ters.

Reading and Writing the PCB

Code that is intended to execute on the Am188EM mi-

crocontroller should perform all writes to the PCB reg-

isters as byte writes. These writes will transfer 16 bits

of data to the PCB register even if an 8-bit register is

named in the instruction. For example, out dx, al re-

sults in the value of ax being written to the port address in

. Reads to the PCB should be done as word reads.

Code written in this manner will run correctly on the

Am188EM microcontroller and on the Am186EM micro-

controller.

Unaligned reads and writes to the PCB result in unpre-

di cta b le beh av ior on both the A m18 6E M an d

Am188EM microcontrollers.

For a complete description of all the registers in the

PCB, see the

Am186EM and Am188EM Microcontrol-

lers User’s Manual, order# 19713.

AM186EM-33VC/W датащи(PDF) 38 Page - Advanced Micro Devices

AM186EM-33VC/W датащи(HTML) 38 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

датащи скачать

ссылки URL