Data Sheet

ADF5902

Rev. 0 | Page 25 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

0

11

1

01

0

0

1

1

0

0

1010

1

0

0

1

1

0

0

1

0

C4(1) C3(0) C2(1) C1(0)

CONTROL

BITS

RESERVED

C5(0)

Figure 35. Register 10 (R10 0x1D32A64A)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

00

00

0

0

0

0

00

0

0

0

0

0

0

0

0

SDR

0

SFT RM1 RM0

RAMP

MODE

0

CR

C4(1) C3(0) C2(1) C1(1)

CONTROL

BITS

RESERVED

C5(0)

CR

0

DISABLED

1

ENABLED

CNTR RESET

RM1

RAMP MODE

0

CONTINUOUS SAWTOOTH

1

RM0

0

1

SINGLE RAMP BURST

10

SINGLE SAWTOOTH BURST

01

CONTINUOUS TRIANGULAR

SFT SING FULL TRI

0DISABLED

1

ENABLED

SDR SD RESET

0

ENABLED

1DISABLED

Figure 36. Register 11 (R11)

REGISTER 10

The bits in Register 10 are reserved and must be programmed

as shown in Figure 35 using a hexadecimal word of 0x1D32A64A.

REGISTER 11

Control Bits

With Bits[C5:C1] set to 01011, Register R11 is programmed.

Figure 36 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB12], Bit DB10, and Bit DB6 are reserved and must

be set as shown in Figure 36.

SD Reset

For most applications, set Bit DB11 to 0. When this bit is set to 0,

the Σ-Δ (SD) modulator is reset on each write to Register R5. If

it is not required that the SD modulator be reset on each write to

Register R5, set this bit to 1.

Single Full Triangle

When Bit DB9 is set to 1, the single full triangle function is

enabled. When Bit DB9 is set to 0, this function is disabled. To

use the single full triangle function, ramp mode (Register 11,

Bits DB[8:7]) must be set to 0b11, single sawtooth burst. For

more information, see the Ramp and Modulation section.

Ramp Mode

Bits[DB8:DB7] determine the type of generated waveform (see

Figure 36). For more information, see the Ramp and

Modulation section.

Counter Reset

Bit DB5 provides a counter reset bit for the counters. Setting

this bit to 1 performs a counter reset of the device counters.

Setting this bit to 0 returns the device to normal operation.

Bit DB5 is shown as CNTR RESET in Figure 36.