AD4112BCPZ datasheet(21/58 Pages) AD

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Data Sheet

AD4112

Rev. A | Page 21 of 58

POWER SUPPLIES

The AD4112 has two independent power supply pins: AVDD,

and IOVDD. The AD4112 has no specific requirements for a

power supply sequence. However, when all power supplies are

stable, a device reset is required. See the AD4112 Reset section

for details on how to reset the device.

AVDD powers the internal 1.8 V analog LDO regulator, which

powers the ADC core. AVDD also powers the crosspoint multi-

plexer and integrated input buffers. AVDD is referenced to AVSS,

and AVDD − AVSS = 3.3 V or 5 V. AVDD and AVSS can be a

single 3.3 V or 5 V supply, or a ±1.65 V or ±2.5 V split supply.

When using split supplies, consider the absolute maximum ratings

(see the Absolute Maximum Ratings section).

IOVDD powers the internal 1.8 V digital LDO regulator. This

regulator powers the digital logic of the ADC IOVDD sets the

voltage levels for the serial peripheral interface (SPI) of the

ADC. IOVDD is referenced to DGND, and IOVDD to DGND

can vary from 2 V (minimum) to 5.5 V (maximum).

Single-Supply Operation (AVSS = DGND)

When the AD4112 is powered from a single supply connected

to AVDD, the supply can be either 3.3 V or 5 V. In this config-

uration, AVSS and DGND can be shorted together on one

single ground plane.

IOVDD can range from 2 V to 5.5 V in this unipolar input

configuration.

DIGITAL COMMUNICATION

The AD4112 has a 3-wire or 4-wire SPI interface that is compatible

with QSPI™, MICROWIRE®, and DSPs. The interface operates in

SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3,

SCLK idles high, the falling edge of SCLK is the drive edge, and

the rising edge of SCLK is the sample edge. Data is clocked out

on the falling/drive edge and data is clocked in on the

rising/sample edge.

DRIVE EDGE

SAMPLE EDGE

Figure 32. SPI Mode 3 SCLK Edges

Accessing the ADC Register Map

The communications register controls access to the full register

map of the ADC. This register is an 8-bit write only register. On

power-up or after a reset, the digital interface defaults to a state

where it is expecting a write to the communications register.

Therefore, all communication begins by writing to the

communications register.

The data written to the communications register determines

which register is being accessed and if the next operation is a

read or write. The RA bits (Bits[5:0] in Register 0x00)

determine the specific register to which the read or write

operation applies.

When the read or write operation to the selected register is

complete, the interface returns to its default state, where it

expects a write operation to the communications register.

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to its default state by resetting the entire device,

including the register contents. Alternatively, if CS is being used

with the digital interface, returning CS high resets the digital

interface to its default state and aborts any current operation.

Figure 33 and Figure 34 show writing to and reading from a

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a

read only register and contains the value 0x30DX for the

AD4112 The communication register and ID register details are

described in Table 10 and Table 11.

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

OR 24 BITS OF DATA

CMD

DATA

Figure 33. Writing to a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on

the Register Selected)

DIN

SCLK

8-BIT COMMAND

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

CMD

DATA

DOUT/RDY

Figure 34. Reading from a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, 24, or 32 Bits; Data Length on DOUT Is

Dependent on the Register Selected)

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