Ver 1.5

17/03/29

3

ES166

LCR/DMM analog front

Test signal amplitude (LC mode)

VR_LC = -600mV

—

0.6

—

Reference voltage temperature

coefficient

100KΩ

resister

Between

VRH

-20℃<TA<70℃

—

75

150

ppm/℃

Note:

1. Full Scale :6000 counts (Max. 6784+2 counts)

2. For best integral linearity of ADC, the metalized polypropylene film capacitor for CINT is necessary.

AC electrical characteristics

Parameter

Symbol

Min.

Typ.

Max.

Unit

SCLK clock frequency

-

-

100

kHz

SCLK clock time “L”

4.7

-

-

us

SLCK clock time “H”

4.0

-

-

SDATA output delay time

0.1

-

3.5

SDATA output hold time

100

-

-

ns

Start condition setup time

4.7

-

-

us

Start condition hold time

4.0

-

-

Data input setup time

200

-

-

ns

Data input hold time

0

-

-

Stop condition setup time

4.7

-

-

us

SCLK/SDATA rising time

-

-

1.0

SCLK/SDATA falling time

-

-

0.3

Bus release time

4.7

-

-

MCU I/O timing diagram

SCLK

SDATA IN

SDATA OUT