CD4017BMS, CD4022BMS

FN3297 Rev 0.00

Page 9 of 10

August 1998

R flip-flop (constructed from two NOR gates of the CD4001B)

generates a reset pulse which clears the CD4017BMS or

put is greater than or equal to 6 in the CD4017BMS or 5 in the

CD4017BMS or CD4022BMS counter section. The “0” decoded

output also goes high at this time. Coincidence of the clock low

and decoded “0” output low resets the S-R flip-flop to enable the

go high and, therefore, cannot be used. In this case “0” decoded

output may be used to perform the clocking function for the next

counter.

FIGURE 11. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

(CLOCK TO CARRY OUT)

FIGURE 12. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF CLOCK INPUT FREQUENCY

FIGURE 13. PROPAGATION DELAY, SETUP, AND RESET

REMOVAL TIME WAVEFORMS

FIGURE 14. DIVIDE BY N COUNTER (N

 10) WITH N DECODED

OUTPUTS

FIGURE 15. CASCADING THE CD4017BMS

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

700

600

500

400

300

200

100

0

10

2030405060

70

8090100

LOAD CAPACITANCE (CL) (pF)

110

CLOCK INPUT FREQUENCY (fCL) (kHz)

10

CL = 50pF

CL = 15pF

LOAD CAPACITANCE

SUPPLY VOLTAGE

(VDD) = 15V

10V

5V

10V

INPUT tr = tf = 20ns

CLOCK

CLOCK

INHIBIT

RESET

DECODE

1-9

DECODE

“0” OR

CARRY

OUTPUT

OUTPUT

TS

TPLH

TPHL

TPHL

TPRHL

TPRLH

Delays Measured Between 50% levels on All Waveforms

CD4017BMS

OR

CD4022BMS

12. . .

N

N DECODED

OUTPUTS

0

CLOCK

CLOCK

INHIBIT

f = CLOCK



FOR N = 2 TO 10

f = CLOCK



O DECODED

OUTPUTS

CD4017BMS

C

CE

Q0 Q1 . . . Q8 Q9

R

CD4017BMS

C

CE

Q0 Q1 . . . Q8 Q9

R

CD4017BMS

C

CE

Q0 Q1 . . . Q8 Q9

R

9 DECODED

OUTPUTS

CLOCK

INTERMEDIATE STAGE

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

LAST STAGE

FIRST STAGE