4

TMP61-Q1

SNIS210 – APRIL 2019

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Copyright © 2019, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings

only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended

OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Voltage across the device

+6

V

Junction temperature

DEC

–65

+150

°C

Junction temperature

LPG

-65

+150

°C

Current through the device

+450

µA

–65

+150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge (DEC)

±1500

V

Electrostatic discharge (LPG)

±2000

V

±750

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Voltage Across Pins 2 (+) and 1 (–)

0

5.5

V

Current passing through the device

0

400

µA

Operating free-air temperature (specified performance) (X1SON/DEC Package)

–40

125

°C

Operating free-air temperature (functional, unspecified performance) (X1SON/DEC Package)

–65

150

°C

Operating free-air temperature (specified performance) (LPG/TO-92S Package)

–40

125

°C

Operating free-air temperature (functional, unspecified performance) (LPG/TO-92S Package)

–65

150

°C

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

For information on self-heating and thermal response time see Layout Guidelines section.

(3)

board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are

included in the PCB, per JESD 51-5.

(4)

Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.4 Thermal Information

TMP6131

UNIT

DEC (X1 SON)

LPG (TO-92)

2 PINS

2 PINS

443.4

TBD

°C/W

Junction-to-case (top) thermal resistance

195.7

TBD

°C/W

Junction-to-board thermal resistance

254.6

TBD

°C/W

Junction-to-top characterization parameter

19.9

TBD

°C/W

Junction-to-board characterization parameter

254.5

TBD

°C/W