MT7697D datasheet(24/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 24 of 84

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2.4.5.1.1

Virtual FIFO

Virtual FIFO DMA is designed to offload the control of the serial interface. The difference between

the virtual FIFO DMA and the full-size/half-size DMA is that the virtual DMA contains an additional

FIFO controller.

The figure below illustrates the operations of virtual FIFO DMA used for UART RX.



READ: DMA controller reads data from UART and increments the WRITE pointer of the FIFO

controller.



WRITE; DMA controller writes data that was area from UART to SRAM in the area defined

before enabling the virtual FIFO.



READ: MCU reads data when FIFO is not empty and the amount of data is over a pre-defined

threshold. The read transaction will be finished only when DMA controller reads back the

data from SRAM.



READ: DMA controller reads data from SRAM and increments the READ pointer of the FIFO

controller.

Figure 2-7. Virtual FIFO Concept

2.4.5.2

DMA Channels and Priority Control

There are two full-size DMA channels, 10 half- size DMA channels, and 13 virtual FIFO DMA channels

in MT7697D.

Table 2-11. DMA Use for Hardware Functions

Hardware Function

DMA Type

Radio (Bluetooth)

Virtual FIFO DMA x 2

DMA

UART

SRAM

MCU

(1) READ

(2) WRITE

(3) READ

(4) READ

memory

FIFO size

Destination Address

READ pointer

(MCU)

WRITE pointer

(UART RX)

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