LTC3370 datasheet(14/44 Pages) LINER

14 / 44 page

LTC3372

Rev. A

For more information www.analog.com

PIN FUNCTIONS

RST (Pin 1): LV Regulator Reset Logic Output. This pin is

pulled low when the feedback pin (FB1-4) voltage of any

enabled LV regulator is outside of its power good window.

The window is –2% to +7.5% (typical) for regulator 1,

and –5% to +7.5% (typical) for regulators 2-4, around

the regulated 0.8V level. This pin is pulled low when all

LV regulators are disabled. Assertion (the pin goes high)

delay is scaled by the CT capacitor.

TEMP (Pin 2): Temperature Indication Pin. TEMP outputs

a voltage of 220mV (typical) at 25°C. The TEMP voltage

will increase by 7mV/°C (typical) at higher temperatures

giving an external indication of the IC’s internal die tem-

perature. The temperature monitor can be shut down by

tying the TEMP pin to INTVCC to reduce quiescent current.

If all LV regulators are disabled, the temperature monitor

shuts down and the TEMP pin becomes high impedance.

EN1 (Pin 3): LV Buck Regulator 1 Enable Input. Active

high. Do not float.

FB1 (Pin 4): LV Buck Regulator 1 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

VINA (Pin 5): LV Power Stage A Input Supply. Bypass to

GND with a 10µF or larger ceramic capacitor.

SWA (Pin 6): LV Power Stage A Switch Node. External

inductor connects to this pin.

SWB (Pin 7): LV Power Stage B Switch Node. External

inductor connects to this pin.

VINB (Pin 8): LV Power Stage B Input Supply. Bypass to

GND with a 10µF or larger ceramic capacitor.

VINC (Pin 9): LV Power Stage C Input Supply. Bypass to

GND with a 10µF or larger ceramic capacitor.

SWC (Pin 10): LV Power Stage C Switch Node. External

inductor connects to this pin.

SWD (Pin 11): LV Power Stage D Switch Node. External

inductor connects to this pin.

VIND (Pin 12): LV Power Stage D Input Supply. Bypass to

GND with a 10µF or larger ceramic capacitor.

FB2 (Pin 13): LV Buck Regulator 2 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

In configurations where LV Regulator 2 is not used, FB2

should be tied to ground.

EN2 (Pin 14): LV Buck Regulator 2 Enable Input. Active

high. In configurations where LV Regulator 2 is not used,

tie EN2 to ground. Do not float.

C1 (Pin 15): LV Regulator Configuration Control Input Bit.

With C2 and C3, C1 configures the buck output current

power stage combinations. C1 should either be tied to

INTVCC or ground. Do not float.

C2 (Pin 16): LV Regulator Configuration Control Input Bit.

With C1 and C3, C2 configures the buck output current

power stage combinations. C2 should either be tied to

INTVCC or ground. Do not float.

C3 (Pin 17): LV Regulator Configuration Control Input Bit.

With C1 and C2, C3 configures the buck output control

power stage combinations. C3 should either be tied to

INTVCC or ground. Do not float.

RT (Pin 18): Oscillator Frequency Pin. This pin provides

twomodesofsettingtheswitchingfrequency.Connectinga

resistorfromRTtogroundwillsettheswitchingfrequency

based on the resistor value. If RT is tied to INTVCC the

internal 2MHz oscillator will be used. Do not float.

PLL/MODE (Pin 19): Oscillator Synchronization Input and

Mode Select Pin. Driving this pin with an external clock

signal synchronizes the internal oscillator to the applied

clock.TheLVbuckssynchronizetotheoscillatorfrequency

and HV buck synchronizes to 1/6th frequency when in

forced continuous mode. When no external clock is ap-

plied the oscillator frequency is programmed by the RT

pin. When not synchronizing to an external clock this input

determines how the controller and regulators operate at

lightload.FloatingorgroundingthispinselectsBurstMode

operation, and tying this pin to INTVCC forces continuous

inductor current mode operation for all the converters and

the controller. Tying this pin to a voltage greater than 1.2V

and less than INTVCC–1.3V selects pulse-skipping mode

operation for the controller, but Burst Mode operation for

the low voltage converters. This pin has a 100k internal

resistor to ground.

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