1.8V Uniform Sector

Standard and Dual Serial Flash

GD25LD80C

19

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and

is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE)

command is not executed if any sector is under protection.

Figure12. Chip Erase Sequence Diagram

7.13.

Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the Deep

Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is no

internal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while

the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since

in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the

Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)

command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI)

command also allows the Device ID of the device to be output on SO.

The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby

Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#

must be driven low for the entire duration of the sequence.

The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes

high. The command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code has

been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires

Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the

cycle that is in progress.

Figure13. Deep Power-Down Sequence Diagram

7.14.

Release from Deep Power-Down / Read Device ID (ABH)

The Release from Power-Down and Read Device ID command is a multi-purpose command, which can be used to

release the device from the Power-Down state or obtain the devices electronic identification (ID) number.

When used to release the device from the Power-Down state, the command is issued by driving the CS# pin low,

shifting the instruction code

“ABH” and driving CS# high as shown in Figure14. Release from Power-Down will take the

Command

0

1

2

3

4

5

6

7

60H or C7H

CS#

SCLK

SI

Command

0

1

2

3

4

5

6

7

B9H

CS#

SCLK

SI

Stand-by mode Deep Power-down mode