GD25B257DFIR datasheet(13/92 Pages) GIGADEVICE

13 / 92 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B257D

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal

Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or

Erase command is accepted.

TB bit

The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom (TB) bit is used to configure the Block Protect area by

BP bit (BP3, BP2, BP1, and BP0), starting from Top or Bottom of the memory array. The TB bit

is defaulted as “0”, which

means Top area protect. When it is set to “1”, the protect area will change to Bottom area of the memory device. This bit is

written with the Write Status Register (WRSR) command.

BP3, BP2, BP1, BP0 bits

The Block Protect (BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.

When the Block Protect (BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protected against

Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP3, BP2, BP1, and BP0)

bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed

only if none sector or block is protected.

QE bit

The Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default value of

QE bit is 1 and it cannot be changed, so that the IO2 and IO3 pins are enabled all the time.

LB3, LB2, LB1 bits.

The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S11, S12, S13) that provide

the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

ECC bit

The on chip ECC engine can be enabled or disabled by the ECC bit. When ECC=1, ECC function is

enabled for all Program and Read operations to ensure data integrity and improve device reliability. Aligned 8-

Byte granularity is required for Program operations, but not for Read operations.

SUS1, SUS2 bits

The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an

Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H)

command as well as a power-down, power-up cycle.

LC1, LC0 bits

The Latency Code (LC) selects the mode and number of dummy cycles between the end of address and the start of

read data output for all read commands.

Some read commands send mode bits following the address to indicate that the next command will be of the same

GD25B257DFIR датащи(PDF) 13 Page - GigaDevice Semiconductor (Beijing) Inc.