GD25B256DFIG datasheet(56/82 Pages) GIGADEVICE

56 / 82 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

7.32.

Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program or sector/block erase operation after

a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the

SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared

from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase

operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a

Program/Erase Suspend is active.

Figure 64 Program/Erase Resume Sequence Diagram

7.33.

Erase Security Registers (44H)

The GD25B256D provides three 2048-Byte Security Registers which can be erased and programmed individually.

These registers may be used by the system manufacturers to store security and other important information separately from

the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 3 or 4-

Byte address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth

bit of the last address Byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon

as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase

Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)

bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers

Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the

Security Registers will be permanently locked; the Erase Security Registers command will be ignored.

Table 18 Security Registers

Address

A23-16

A15-12

A11

A10-0

Security Register #1

00H

0 0 0 1

Don’t care

Security Register #2

00H

0 0 1 0

Don’t care

Security Register #3

00H

0 0 1 1

Don’t care

Command

7AH

CS#

SCLK

Resume Erase/Program

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