TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT

TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

19

POST OFFICE BOX 655303

APPLICATION INFORMATION

programming the TPS77x01 adjustable LDO regulator

The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as

shown in Figure 24. The output voltage is calculated using:

V

O +

V

ref

1

) R1

R2

(1)

Where:

Resistors R1 and R2 should be chosen for approximately 50-

µA divider current. Lower value resistors can be

used but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage

currents at FB increase the output voltage error. The recommended design procedure is to choose

R2 = 30.1 k

Ω to set the divider current at 50 µA and then calculate R1 using:

R1

+

V

O

V

ref

* 1

R2

(2)

OUTPUT

VOLTAGE

R1

R2

2.5 V

3.3 V

3.6 V

UNIT

33.5

53.8

61.5

30.1

30.1

30.1

k

Ω

k

Ω

k

Ω

OUTPUT VOLTAGE

PROGRAMMING GUIDE

VO

VI

PG or

RESET

OUT

FB/SENSE

R1

R2

GND

EN

IN

TPS77x01

PG or RESET Output

0.1

µF

250 k

Ω

CO

NOTE: To reduce noise and prevent

oscillation, R1 and R2 need to be as

close as possible to the FB/SENSE

terminal.

Figure 24. TPS77x01 Adjustable LDO Regulator Programming