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SC284P датащи(PDF) 20 Page - Semtech Corporation |
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SC284P датащи(HTML) 20 Page - Semtech Corporation |
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20 / 22 page ![]() 20 SC284P Figure 8 — PCB Bottom Layer Applications Information (continued) PCB Layout Considerations The layout diagram in Figure 7 shows a recommended PCB top layer for the SC284P and supporting components. Figure 8 shows the bottom layer for this PCB. Fundamental layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the perfor- mance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. The following guidelines are recommended when devel- oping a PCB layout: The input capacitor, C IN, should be placed as close to the VIN and PGND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to connect as closely to the IC as possible. This will minimize EMI and input voltage ripple by localizing the high frequency current pulses. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. C OUT and L should be connected as close as possible between the LX and PGND pins, with a direct return to the PGND pin from C OUT. Route the output voltage feedback/sense path away from the inductor and LX node to minimize noise and magnetic interference. Use a ground plane referenced to the SC284P PGND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. If possible, minimize the resistance from the output and PGND pin to the load. This will reduce the voltage drop on the ground plane and improve the load regulation. It will also improve the overall efficiency by reducing the copper losses on the output and ground planes. Connect the AGND pins to the thermal pad. . 2. 3. 4. 5. 6. Figure 7 — Recommended PCB Layout (Top Layer) U1 C2 U1 R2 U1 C4 U1 C5 U1 L2 U1 C1 U1 R1 U1 C6 U1 L1 U1 C3 U1 Figure 9 — Recommended PCB Layout (Top Layer Details) |
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