M48T86PC1F datasheet(13/29 Pages) ARTSCHIP

13 / 29 page

13/29

M48T86

Periodic Interrupt

The periodic interrupt will cause the IRQ pin to go

to an active state from once every 500ms to once

every 122µs. This function is separate from the

alarm interrupt which can be output from once per

second to once per day. The periodic interrupt rate

is selected using the same Register A bits which

select the square wave frequency (see Table

4., page 14). Changing the Register A bits affects

both the square wave frequency and the periodic

interrupt output. However, each function has a

separate enable bit in Register B. The periodic in-

terrupt is enabled by the PIE Bit (Register B; Bit 6).

The periodic interrupt can be used with software

counters to measure inputs, create output inter-

vals, or await the next needed software function.

Alarm Interrupt

The alarm interrupt provides the system processor

with an interrupt when a match is made between

the RTC's hours, minutes, and seconds bytes and

the corresponding alarm bytes.

The three alarm bytes can be used in two ways.

First, when the alarm time is written in the appro-

priate hours, minutes, and seconds alarm loca-

tions, the alarm interrupt is initiated at the specified

time each day if the Alarm Interrupt Enable Bit

(Register B; Bit 5) is high. The second use is to in-

sert a “Don't care” state in one or more of the three

alarm bytes. The “Don't care” code is any hexa-

decimal value from C0 to FF. The two most signif-

icant bits of each byte set the “Don't care”

condition when at logic '1.' An alarm will be gener-

ated each hour when the “Don't care” is are set in

the hours byte. Similarly, an alarm is generated

every minute with “Don't care” codes in the hour

and minute alarm bytes. The “Don't care” codes in

all three alarm bytes create an interrupt every sec-

ond.

Update Cycle Interrupt

After each update cycle, the Update Cycle Ended

Flag Bit (UF) (Register C; Bit 4) is set to a '1.' If the

Update Interrupt Enable Bit (UIE) (Register B; Bit

4) is set to a '1,' and the SET Bit (Register B; Bit 7)

is a '0,' then an interrupt request is generated at

the end of each update cycle.

Oscillator Control Bits

When the M48T86 is shipped from the factory the

internal oscillator is turned off. This feature pre-

vents the lithium energy cell from being dis-

charged until it is installed in a system. A pattern of

“010” in Bits 4-6 of Register A will turn the oscillator

on and enable the countdown chain. A pattern of

“11X” will turn the oscillator on, but holds the

countdown chain of the oscillator in reset. All other

combinations of Bits 4-6 keep the oscillator off.

Update Cycle

The M48T86 executes an update cycle once per

second regardless of the SET Bit (Register B; Bit

7). When the SET Bit is asserted, the user copy of

the double buffered time, calendar, and alarm

bytes is frozen and will not update as the time in-

crements. However, the time countdown chain

continues to update the internal copy of the buffer.

This feature allows accurate time to be main-

tained, independent of reading and writing the

time, calendar, and alarm buffers. This also guar-

antees that the time and calendar information will

be consistent. The update cycle also compares

each alarm byte with the corresponding time byte

and issues an alarm if a match or if a “Don't care”

code is present in all three positions.

There are three methods of accessing the real

time clock that will avoid any possibility of obtain-

ing inconsistent time and calendar data. The first

method uses the update-ended interrupt. If en-

abled, an interrupt occurs after every update cycle

which indicates that over 999ms are available to

read valid time and date information. If this inter-

rupt is used, the IRQF Bit (Register C; Bit 7) should

be cleared before leaving the interrupt routine.

A second method uses the Update-In-Progress

(UIP) Bit (Register A; Bit 7) to determine if the up-

date cycle is in progress. The UIP Bit will pulse

once per second. After the UIP Bit goes high, the

update transfer occurs 244µs later. If a low is read

on the UIP Bit, the user has at least 244µs before

the time/calendar data will be changed. Therefore,

the user should avoid interrupt service routines

that would cause the time needed to read valid

time/calendar data to exceed 244µs.

The third method uses a periodic interrupt to deter-

mine if an update cycle is in progress. The UIP Bit

is set high between the setting of the PF Bit (Reg-

ister C; Bit 6). Periodic interrupts that occur at a

rate greater than tBUC allow valid time and date in-

formation to be reached at each occurrence of the

periodic interrupt.The READs should be complet-

ed within 1/(tPL/2 + tBUC) to ensure that data is not

read during the update cycle.

M48T86PC1F датащи(PDF) 13 Page - ARTSCHIP ELECTRONICS CO.,LMITED.

M48T86PC1F датащи(HTML) 13 Page - ARTSCHIP ELECTRONICS CO.,LMITED.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

датащи скачать

ссылки URL