AW2013

Nov 2017 V1.5

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d)

Master sends control register address (8-bit)

e)

Slave sends acknowledge signal

f)

Master sends data byte to be written to the addressed register

g)

Slave sends acknowledge signal

h)

If master will send further data bytes the control register address will be incremented by one

after acknowledge signal (repeat step 6,7)

i)

Master generates STOP condition to indicate write cycle end

0

A2 A1 A0

A6 A5

A3

A4

A4 A3

A1

A2

A7

A5

A6

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

D5 D4

D2

D3

A0

D6

D7

D6

D0

D1

D1 D0

D7

7

8

0

1

2

3

4

5

6

7

8

0

1

...

6

SCL

SDA

Ack

Ack

Ack

7

8

Ack

START

R/W

STOP

device address

register address

register data 1

register data2

Figure 5 I2C write cycle, multiple registers are written

6.3.2

Read Cycle

In a read cycle, the following steps should be followed:

j)

Master device generates START condition

k)

Master device sends slave address (7-bit) and the data direction bit (r/w = 0).

l)

Slave device sends acknowledge signal if the slave address is correct.

m) Master sends control register address (8-bit)

n)

Slave sends acknowledge signal

o)

Master generates STOP condition followed with START condition or REPEAT START condition

p)

Master device sends slave address (7-bit) and the data direction bit (r/w = 1).

q)

Slave device sends acknowledge signal if the slave address is correct.

r)

Slave sends data byte from addressed register.

s)

If the master device sends acknowledge signal, the slave device will increase the control

register address by one, then send the next data from the new addressed register.

t)

If the master device generates STOP condition, the read cycle is ended.