GS3281 datasheet(21/97 Pages) SEMTECH

21 / 97 page

GS3281

Final Data Sheet

Rev.7

PDS-061453

January 2019

21 of 97

Semtech

Proprietary & Confidential

www.semtech.com

Table 4-3: CDR Control and Status Parameters

and Name

Parameter Name

Description

06,

RATE_ DETECT_ MODE

CFG_AUTO_RATE_DETECT_ENA

Enables or disables the automatic rate detection mode

of the CDR.

CFG_MANUAL_RATE

Select a single rate for CDR rate detection when

CFG_AUTO_RATE_DETECT_ENA is 0b.

CFG_RATE_ENA_3G

3G auto rate detection enable

CFG_RATE_ENA_HD

HD auto rate detection enable

CFG_RATE_ENA_SD

SD auto rate detection enable

CFG_RATE_ENA_MADI

MADI auto rate detection enable

08,

REF_CLK_ MODE

CFG_REF_CLK_MODE_MANUAL

Enables or disables external reference clock mode.

0B,

PLL_LOOP_

BANDWIDTH_ 1

CFG_PLL_LBW_3G

Configures the Loop Bandwidth for 3G signals.

CFG_PLL_LBW_HD

Configures the Loop Bandwidth for HD signals.

0C,

PLL_LOOP_

BANDWIDTH_ 2

CFG_PLL_LBW_SD

Configures the Loop Bandwidth for SD signals.

CFG_PLL_LBW_MADI

Configures the Loop Bandwidth for MADI signals.

11,

GPIO1_CFG

CFG_GPIO1_FUNCTION

Sets the function of GPIO1.

CFG_GPIO1_OUTPUT_ ENA

Sets the GPIO pin as either an output or an input.

85,

STICKY_ COUNTS_1

STAT_CNT_PLL_LOCK_CHANGES

Counter showing the number of times the PLL lock

status changed.

STAT_CNT_RATE_CHANGES

Counter showing the number of times the PLL lock rate

changed.

86,

CURRENT_ STATUS_0

STAT_LOCK

The status of the PLL. Locked, or unlocked.

87,

CURRENT_ STATUS_1

STAT_DETECTED_RATE

The rate at which the PLL is locked to.

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