2

CPWR-AN10, REV -C

SiC MOSFET Isolated Gate Driver

This document is provided for informational purposes only and is not a warranty or a specification.

For product specifications, please see the data sheets available at www.cree.com/power. For warranty

information, please contact Cree Sales at PowerSales@cree.com.

Figure 3: Isolated Gate Driver Schematic

Theseconvertersareinexpensivewithanisolationvoltageratingof5.2kVandalsohaveverylow

isolationcapacitance.Inthisparticularconfiguration,X2isa12Vin5VoutconverterandX3is

a12Vin,+/-12Voutconverter.Asshownintheschematic,theoutputsoftheconvertersare

series connected and the common connection is referenced to the source terminal. Therefore, VCC

determines the gate pulse positive voltage and –VEE determines the negative gate pulse voltage. The

–VEE node is used as the ground reference for opto-isolator and the gate driver. The opto-isolator’s

maximumoperatingvoltageis20VwhichcanbegreaterthanthevoltageappearingatVCC.An

emitter follower clam consisting of Q1 and D1 has been added to limit the voltage to the opto-isolator

to17.3Vnominal.Abaseresistor(R16)wasincludedifadditionaldampeningisdesiredforthe

emitterfollower.Inpractice,azeroohmresistorworksfine.ResistorsR2,R4,R5,R9-R15anddiode

D2canbepopulatedtoprovideoptimumturn-onandturn-offperformance.Inthiscase,onlyR2,R4

andR5arepopulatedwith20ohm1/3wattresistors.Tominimizestrayinductance,capacitorsC8-

C10 are located very close to the source output pin and the gate driver to provide very tight coupling

between the source output terminal and the –VEE node.

THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE

0.100" ISOLATION

BOUNDRY SLIT

BOARD IF REQ.

VCC HIGH

INPUT HIGH

VCC HIGH RTN

INPUT LOW

VCC LOW

VCC LOW RTN

U2

IXDN609SI

VCC

1

IN

2

NC

3

GND

4

VCC

8

OUT

7

OUT

6

GND

5

J2

HEADER 6

1

2

3

4

5

6

C2

1U

0603

C7

4.7U

1206

U1

ACPL-4800-300E

NC

1

ANODE

2

CATH

3

NC

4

VCC

8

NC

7

VO

6

GND

5

C10

R6 620

0805

C3

1U

0603

C6

100N

0805

R3 620

0805

R7

47K

0603

C4

TBD

0805

R14

20

C8

R8

47K

0603

X2

RP-1205S

+VIN

1

-VIN

2

-VOUT

5

+VOUT

7

Q1

DXT2222A

R12

20

D2

DIODE

R1

10K

0805

JP1

HEADER 3

7

8

9

C5

100N

0805

X3

RP-1212D

+VIN

1

-VIN

2

-VOUT

5

COM

6

+VOUT

7

R15

20

JP2

HEADER 3

10

11

12

C9

100N

C1

1U

0603

D1

MMSZ5248B-7-F

R13

20

VCC LOW

INPUT LOW

INPUT HIGH

VCC LOW RTN

VCC HIGH

SOURCE

GATE

+VCC

VCC HIGH RTN

-VEE

-VEE

-VEE

-VEE

-VEE

-VEE

SOURCE

-VEE

+VCC

SOURCE

-VEE

+VCC

-VEE

-VEE

R16 0

0805

Operationofthegatedriverisasfollows.A+10to+12Vpulseisappliedtotheoptocausesthe

gateterminaltogohigh.Theintentofthiscircuitistoaffordthemaximumflexibility.Therefore,

unregulated DC-DC converters were used so that the output gate pulse positive and negative voltage

levels can be adjusted at ground level. The gate voltage positive level is adjusted by varying the

voltage between the VCC HIGH and VCC HIGH RTN and the negative pulse level is adjusted by varying

the voltage between the VCC LOW and VCC LOW RTN pins. The procedure is to observe the output

of the gate driver board with an oscilloscope and adjust VCC HIGH and VCC LOW input voltages until

thegatepulseissettothedesiredvalues.Caremustbetakenduringadjustmenttoinsurethatthe

voltagebetweentheVCCand–VEEnodesdoesnotexceedthemaximumratingsofU2,whichis35V.