DS563F2

17

CS5381

3.5

High-Pass Filter and DC Offset Calibration

The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into the

A/D converter. The CS5381 includes a high-pass filter after the decimator to remove any DC offset which

could result in recording a DC level, possibly yielding “clicks” when switching between devices in a multi-

channel system.

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen

and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible

to perform a system DC offset calibration by:

1.

Running the CS5381 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-

acteristics for filter settling time.

2.

Disabling the high-pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the

calibration point and the CS5381.

VQ

+

634

Ω

634

Ω

91

Ω

91

Ω

+

-

-

2700 pF

470 pF

470 pF

COG

COG

10 uF

10 uF

ADC AIN+

ADC AIN-

AIN+

AIN-

COG

100 k

Ω

10 k

Ω

10 k

Ω

100 k

Ω

Figure 24. Recommended Analog Input Buffer