RM3182
PRODUCT SPECIFICATION
4
Principles of Operation
Each device consists of one differential driver and associated
gating circuitry. The gating circuitry consists of clock and
sync signal inputs which are ANDed with the two data
inputs. See the block diagram and truth table. Three power
supplies are required to operate the RM3182 in a typical
ARINC 429 bus application: +15V, -15V, and +5V. The +5V
supply, in addition to powering the internal bus current
regulator, provides a reference voltage that determines the
output voltage swing. The differential output swing will
equal 2 VREF. If a value of VREF other than +5V is used,
then a separate +5V supply is required for pin V1.
Figure 1 depicts connections for the ARINC 429 application.
The driver output impedance is nominally 75
Ω. With the
Data(A) input at a logic high and Data (B) input at a logic
low, AOUT will swing to +VREF and BOUT will swing to
VREF (constituting a logic high state). Reversing the data
input states will cause AOUT to swing to -VREF and BOUT
to +VREF. With both data input signals at a logic low state,
the outputs will both swing to 0V (output in null state).
The slew rate of the outputs, and consequently rise and fall
times, can be adjusted through the selection of two external
capacitor values. Typical values are CA = CB = 75 pF for
high-speed operation (100 Kbits/sec) and CA = CB = 500 pF
for low-speed operation (12.5 to 14 Kbits/sec).
The device can be powered down by applying a logic high
signal to the Power Enable pin. If the power down feature is
not used, then the Power Enable pin should be tied directly
to ground.
Figure 1. ARINC 429 Bus Application
Data (A)
Data (B)
V
REF
V1
Sync
Clock
A
C
C
Gnd
Power
Enable
-V
S
B
Inputs
To Bus
4
13
+5V
+15V
-15V
RM3182
1
16
3
14
9
5
12
8
2
7
11
6
65-3182-04
OUT
OUT
A
B
+V
S
Note: Pin numbers are for
the 16-lead DIP.
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